TXS=ENDPOINT_OK_, RXS=ENDPOINT_OK_
Endpoint control 0
| RXS | Rx endpoint stall 0 (ENDPOINT_OK_): Endpoint ok. 1 (ENDPOINT_STALLED_SOF): Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1] |
| RESERVED | Reserved |
| RXT | Endpoint type Endpoint 0 is always a control endpoint. |
| RESERVED | Reserved |
| RXE | Rx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1. |
| RESERVED | Reserved |
| TXS | Tx endpoint stall 0 (ENDPOINT_OK_): Endpoint ok. 1 (ENDPOINT_STALLED_SOF): Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue returning STALL until the bit is cleared by software, or it will automatically be cleared upon receipt of a new SETUP request. After receiving a SETUP request, this bit will continue to be cleared by hardware until the associated ENDSETUPSTAT bit is cleared.[1] |
| RESERVED | Reserved |
| TXT | Endpoint type Endpoint 0 is always a control endpoint. |
| RESERVED | Reserved |
| TXE | Tx endpoint enable Endpoint enabled. Control endpoint 0 is always enabled. This bit is always 1. |
| RESERVED | Reserved |